The article, "Thin Film Multichip Modules", G. Messner, I. Turlik, J. Balde, P. Garrou, International Society for Hybrid Microelectronics, 1992 discusses a number of processes which are representative of current multi-chip module, deposited (MCM-D) manufacture. All of these processes utilize photolithography in defining at least one of the layers, either of the conductive or dielectric variety.
FIG. 1 illustrates the 5 step process for photolithographic patterning of a dielectric layer. Photolithographic patterning of metal layers involves a similar sequence of steps.
Referring to FIG. 1A, substrate S has previously patterned metal M deposited thereon. Deposition of dielectric D to be patterned has occurred. Proceeding to FIG. 1B, photoresist P is deposited. At FIG. 1C, an image causes the photoresist to be exposed at intervals 14. Development occurs with removal of photoresist from intervals 14 in FIG. 1D. This is followed by etch of the dielectric to leave dielectric channels 15 in FIG. 1E followed by the stripping of the photoresist in FIG. 1F.
The reader will understand that had photoimageable polyimide been used instead of photoresist, only the expose and develop steps of FIGS. 1C and 1D would have been utilized.
The repeating of the sequence of photolithographic steps similar to those set forth above is required for the fabrication of multichip modules. For example, multichip module constructions are known which have sixteen (16) layers.
It can therefore be understood that one drawback of photolithographic processing is that multiple steps (2 for photo-imageable polyimide, 5 when photoresist is used) intervene between depositing the layer to be patterned and the resulting permanent structures impressed in that layer. The number of process steps reduces yields and makes process monitoring and trouble shooting difficult.
Photolithographic processes of various complexity are utilized in the prior art. For example, from the above "Thin Film Multichip Modules", a summary has been prepared of the number of processes steps per metal/dielectric layer required by different manufacturer's processes. This summary is presented in tabular form herein:
______________________________________ Steps per Metal/Dielectric Process Layer ______________________________________ GE 8 MCNC 14 MCC 15 Tektronix 15 NTT 10 RPI 11 CNET 10 Alcoa 15 Polycon 12 ______________________________________
Table 1--List of number of process steps required by different manufacturers to deposit and pattern a single MCM-D metal and dielectric layer.
A greater number of process steps translates directly into lower throughput and larger amounts of work in progress for the manufacturer.
MCM-Ds offer the greatest potential performance of current MCM technologies. However, a principal barrier to wider spread use has been the cost and complexity required for their construction utilizing the conventional photolithographic techniques.